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? semiconductor components industries, llc, 2002 april, 2002 rev. 5 1 publication order number: mc10e195/d mc10e195, mc100e195 5vecl programmable delay chip the mc10e/100e195 is a programmable delay chip (pdc) designed primarily for clock de-skewing and timing adjustment. it provides variable delay of a differential ecl input transition. the delay section consists of a chain of gates organized as shown in the logic symbol. the first two delay elements feature gates that have been modified to have delays 1.25 and 1.5 times the basic gate delay of approximately 80 ps. these two elements provide the e195 with a digitally-selectable resolution of approximately 20 ps. the required device delay is selected by the seven address inputs d[0:6], which are latched on chip by a high signal on the latch enable (len) control. because the delay programmability of the e195 is achieved by purely differential ecl gate delays the device will operate at frequencies of >1.0 ghz while maintaining over 600 mv of output swing. the e195 thus offers very fine resolution, at very high frequencies, that is selectable entirely from a digital input allowing for very accurate system clock timing. an eighth latched input, d7, is provided for cascading multiple pdc's for increased programmable range. the cascade logic allows full control of multiple pdc's, at the expense of only a single added line to the data bus for each additional pdc, without the need for any external gating. the v bb pin, an internally generated voltage supply, is available to this device only. for single-ended input conditions, the unused differential input is connected to v bb as a switching reference voltage. v bb may also rebias ac coupled inputs. when used, decouple v bb and v cc via a 0.01 f capacitor and limit current sourcing or sinking to 0.5 ma. when not used, v bb should be left open. the 100 series contains temperature compensation. ? 2.0 ns worst case delay range ? 20 ps/delay step resolution ? >1.0 ghz bandwidth ? on chip cascade circuitry ? pecl mode operating range: v cc = 4.2 v to 5.7 v with v ee = 0 v ? necl mode operating range: v cc = 0 v with v ee = 4.2 v to 5.7 v ? internal input pulldown resistors ? esd protection: > 2 kv hbm, > 200 v mm ? meets or exceeds jedec spec eia/jesd78 ic latchup test ? moisture sensitivity level 1 for additional information, see application note and8003/d ? flammability rating: ul94 code v0 @ 1/8o, oxygen index 28 to 34 ? transistor count = 368 devices device package shipping ordering information mc10e195fn plcc28 37 units/rail mc10e195fnr2 plcc28 500 units/reel mc100e195fn plcc28 37 units/rail mc100e195fnr2 plcc28 500 units/reel marking diagrams a = assembly location wl = wafer lot yy = year ww = work week plcc28 fn suffix case 776 mc10e195fn awlyyww mc100e195fn awlyyww 128 128 http://onsemi.com
mc10e195, mc100e195 http://onsemi.com 2 pin description pin function in/in en d[0:7] q/q len set min set max cascade, cascade v bb v cc , v cco v ee nc ecl signal input ecl input enable ecl mux select inputs ecl signal output ecl latch enable ecl min delay set ecl max delay set ecl cascade signal reference voltage output positive supply negative supply no connect 1 logic diagram simplified v bb in in en len set min set max 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 111 1 0 1 q q cascade cascade cascade 7 bit latch len q latch d 4 gates 8 gates 16 gates * 1.25 * 1.5 d0 d1 d2 d3 d4 d5 d6 d7 * delays are 25% or 50% longer than * standard (standard 80 ps) v ee d2 d3 d4 d5 d6 d7 nc nc nc en set min set max cascade cascade nc nc v cc v cco q q v cco d1 d0 len v ee in in v bb 25 24 23 22 21 20 19 26 27 28 1 2 3 4 18 17 16 15 14 13 12 56 7891011 pinout:28-lead plcc (top view) logic diagram and pinout assignment warning: all v cc , v cco , and v ee pins must be externally connected to power supply to guarantee proper operation. * all v cc and v cco pins are tied together on the die.
mc10e195, mc100e195 http://onsemi.com 3 maximum ratings (note 1) symbol parameter condition 1 condition 2 rating units v cc pecl mode power supply v ee = 0 v 8 v v ee necl mode power supply v cc = 0 v 8 v v i pecl mode input voltage v ee = 0 v v i v cc 6 v v i pecl mode in ut voltage necl mode input voltage v ee 0 v v cc = 0 v v i v cc v i v ee 6 6 v v i out output current continuous surge 50 100 ma ma i bb v bb sink/source 0.5 ma ta operating temperature range 0 to +85 c t stg storage temperature range 65 to +150 c q ja thermal resistance (junction to ambient) 0 lfpm 500 lfpm 28 plcc 28 plcc 63.5 43.5 c/w c/w q jc thermal resistance (junction to case) std bd 28 plcc 22 to 26 c/w v ee pecl operating range necl operating range 4.2 to 5.7 5.7 to 4.2 v v t sol wave solder <2 to 3 sec @ 248 c 265 c 1. maximum ratings are those values beyond which device damage may occur. 10e series pecl dc characteristics v ccx = 5.0 v; v ee = 0.0 v (note 1) 0 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit i ee power supply current 130 156 130 156 130 156 ma v oh output high voltage (note 2) 3980 4070 4160 4020 4105 4190 4090 4185 4280 mv v ol output low voltage (note 2) 3050 3210 3370 3050 3210 3370 3050 3227 3405 mv v ih input high voltage (single ended) 3830 3995 4160 3870 4030 4190 3940 4110 4280 mv v il input low voltage (single ended) 3050 3285 3520 3050 3285 3520 3050 3302 3555 mv v bb output voltage reference 3.62 3.63 3.65 3.75 3.69 3.81 v v ihcmr input high voltage common mode range (differential) (note 3) tbd tbd tbd v i ih input high current 150 150 150 m a i il input low current 0.5 0.3 0.5 0.25 0.3 0.2 m a note: devices are designed to meet the dc specifications shown in the above table, after thermal equilibrium has been establishe d. the circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained. 1. input and output parameters vary 1:1 with v cc . v ee can vary +0.46 v / 0.06 v. 2. outputs are terminated through a 50 ohm resistor to v cc 2 volts. 3. v ihcmr min varies 1:1 with v ee , max varies 1:1 with v cc . 10e series necl dc characteristics v ccx = 0.0 v; v ee = 5.0 v (note 1) 0 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit i ee power supply current 130 156 130 156 130 156 ma v oh output high voltage (note 2) 1020 930 840 980 895 810 910 815 720 mv v ol output low voltage (note 2) 1950 1790 1630 1950 1790 1630 1950 1773 1595 mv v ih input high voltage (single ended) 1170 1005 840 1130 970 810 1060 890 720 mv v il input low voltage (single ended) 1950 1715 1480 1950 1715 1480 1950 1698 1445 mv v bb output voltage reference 1.38 1.37 1.35 1.25 1.31 1.19 v v ihcmr input high voltage common mode range (differential) (note 3) tbd tbd tbd v i ih input high current 150 150 150 m a i il input low current 0.5 0.3 0.5 0.065 0.3 0.2 m a note: devices are designed to meet the dc specifications shown in the above table, after thermal equilibrium has been establishe d. the circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained. 1. input and output parameters vary 1:1 with v cc . v ee can vary +0.46 v / 0.06 v. 2. outputs are terminated through a 50 ohm resistor to v cc 2 volts. 3. v ihcmr min varies 1:1 with v ee , max varies 1:1 with v cc .
mc10e195, mc100e195 http://onsemi.com 4 100e series pecl dc characteristics v ccx = 5.0 v; v ee = 0.0 v (note 1) 0 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit i ee power supply current 130 156 130 156 150 179 ma v oh output high voltage (note 2) 3975 4050 4120 3975 4050 4120 3975 4050 4120 mv v ol output low voltage (note 2) 3190 3295 3380 3190 3255 3380 3190 3260 3380 mv v ih input high voltage (single ended) 3835 4050 4120 3835 4120 4120 3835 4120 4120 mv v il input low voltage (single ended) 3190 3300 3525 3190 3525 3525 3190 3525 3525 mv v bb output voltage reference 3.62 3.74 3.62 3.74 3.62 3.74 v v ihcmr input high voltage common mode range (differential) (note 3) tbd tbd tbd v i ih input high current 150 150 150 m a i il input low current 0.5 0.3 0.5 0.25 0.5 0.2 m a note: devices are designed to meet the dc specifications shown in the above table, after thermal equilibrium has been establishe d. the circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained. 1. input and output parameters vary 1:1 with v cc . v ee can vary +0.46 v / 0.8 v. 2. outputs are terminated through a 50 ohm resistor to v cc 2 volts. 3. v ihcmr min varies 1:1 with v ee , max varies 1:1 with v cc . 100e series necl dc characteristics v ccx = 0.0 v; v ee = 5.0 v (note 1) 0 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit i ee power supply current 130 156 130 156 150 179 ma v oh output high voltage (note 2) 1025 950 880 1025 950 880 1025 950 880 mv v ol output low voltage (note 2) 1810 1705 1620 1810 1745 1620 1810 1740 1620 mv v ih input high voltage (single ended) 1165 950 880 1165 880 880 1165 880 880 mv v il input low voltage (single ended) 1810 1700 1475 1810 1475 1475 1810 1475 1475 mv v bb output voltage reference 1.38 1.26 1.38 1.26 1.38 1.26 v v ihcmr input high voltage common mode range (differential) (note 3) tbd tbd tbd v i ih input high current 150 150 150 m a i il input low current 0.5 0.3 0.5 0.25 0.5 0.2 m a note: devices are designed to meet the dc specifications shown in the above table, after thermal equilibrium has been establishe d. the circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained. 1. input and output parameters vary 1:1 with v cc . v ee can vary +0.46 v / 0.8 v. 2. outputs are terminated through a 50 ohm resistor to v cc 2 volts. 3. v ihcmr min varies 1:1 with v ee , max varies 1:1 with v cc .
mc10e195, mc100e195 http://onsemi.com 5 ac characteristics v ccx = 5.0 v; v ee = 0.0 v or v ccx = 0.0 v; v ee = 5.0 v (note 1) 0 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit f max maximum toggle frequency > 1.0 ghz t plh t phl propagation delay in to q; tap = 0 in to q; tap = 127 en to q; tap = 0 d7 to cascade 1210 3200 1250 300 1360 3570 1450 450 1510 3970 1650 700 1240 3270 1275 300 1390 3630 1475 450 1540 4030 1675 700 1440 3885 1350 300 1590 4270 1650 450 1765 4710 1950 700 ps t range programmable range t pd (max) t pd (min) 2000 2175 2050 2240 2375 2580 ps d t step delay (note 6.) d0 high d1 high d2 high d3 high d4 high d5 high d6 high 55 115 250 505 1000 17 34 68 136 272 544 1088 105 180 325 620 1190 55 115 250 515 1030 17.5 35 70 140 280 560 1120 105 180 325 620 1220 65 140 305 620 1240 21 42 84 168 336 672 1344 120 205 380 740 1450 ps lin linearity (note 7.) d1 d0 d1 d0 d1 d0 t skew duty cycle skew t phl t plh (note 1.) 30 30 30 ps t jitter cycletocycle jitter tbd tbd tbd ps t s setup time d to len d to in (note 2.) en to in (note 3.) 200 800 200 0 200 800 200 0 200 800 200 0 ps t h hold time len to d in to en (note 4.) 500 0 250 500 0 250 500 0 250 ps t r release time en to in (note 5.) set max to len set min to len 300 800 800 300 800 800 300 800 800 ps t jit jitter (note 8.) <5.0 <5.0 <5.0 ps t r t f output rise/fall time 2080% (q) 2080% (cascade) 125 300 225 450 325 650 125 300 225 450 325 650 125 300 225 450 325 650 ps 1. 10 series: v ee can vary +0.46 v / 0.06 v. 100 series: v ee can vary +0.46 v / 0.8 v. 1. duty cycle skew guaranteed only for differential operation measured from the cross point of the input to the cross point of t he output. 2. this setup time defines the amount of time prior to the input signal the delay tap of the device must be set. 3. this setup time is the minimum time that en must be asserted prior to the next transition of in/in to prevent an output response greater than 75 mv to that in/in transition. 4. this hold time is the minimum time that en must remain asserted after a negative going in or positive going in to prevent an output response greater than 75 mv to that in/in transition. 5. this release time is the minimum time that en must be deasserted prior to the next in/in transition to ensure an output response that meets the specified in to q propagation delay and transition times. 6. specification limits represent the amount of delay added with the assertion of each individual delay control pin. the various combinations of asserted delay control inputs will typically realize d0 resolution steps across the specified programmable range. 7. the linearity specification guarantees to which delay control input the programmable steps will be monotonic (i.e. increasing delay steps for increasing binary counts on the control inputs dn). typically the device will be monotonic to the d0 input, however under worst case conditions and process variation, delays could decrease slightly with increasing binary counts when the d0 input is the lsb. with the d1 input as the lsb the device is guaranteed to be monotonic over all specified environmental conditions and process variation. 8. the jitter of the device is less than what can be measured without resorting to very tedious and specialized measurement tech niques.
mc10e195, mc100e195 http://onsemi.com 6 v cco address bus (a0-a6) a7 input d1 d0 len v ee in in v bb d2 d3 d4 d5 d6 d7 en set min set max cascade cascade v cc v cco q q d1 d0 len v ee in in v bb en set min set max cascade cascade v cc v cco q q v cco output d2 d3 d4 d5 d6 d7 e195 chip #1 e195 chip #2 figure 1. cascading interconnect architecture cascading multiple e195's to increase the programmable range of the e195 internal cascade circuitry has been included. this circuitry allows for the cascading of multiple e195's without the need for any external gating. furthermore this capability requires only one more address line per added e195. obviously cascading multiple pdc's will result in a larger programmable range however this increase is at the expense of a longer minimum delay. figure 1 illustrates the interconnect scheme for cascading two e195's. as can be seen, this scheme can easily be expanded for larger e195 chains. the d7 input of the e195 is the cascade control pin. with the interconnect scheme of figure 1 when d7 is asserted it signals the need for a larger programmable range than is achievable with a single device. an expansion of the latch section of the block diagram is pictured below. use of this diagram will simplify the explanation of how the cascade circuitry works. when d7 of chip #1 above is low the cascade output will also be low while the cascade bar output will be a logical high. in this condition the set min pin of chip #2 will be asserted and thus all of the latches of chip #2 will be reset and the device will be set at its minimum delay. since the reset and set inputs of the latches are overriding any changes on the a0a6 address bus will not affect the operation of chip #2. chip #1 on the other hand will have both set min and set max de-asserted so that its delay will be controlled entirely by the address bus a0a6. if the delay needed is greater than can be achieved with 31.75 gate delays (1111111 on the a0a6 address bus) d7 will be asserted to signal the need to cascade the delay to the next e195 device. when d7 is asserted the set min pin of chip #2 will be de-asserted and the delay will be controlled by the a0a6 address bus. chip #1 on the other hand will have its set max pin asserted resulting in the device delay to be independent of the a0a6 address bus. when the set max pin of chip #1 is asserted the d0 and d1 latches will be reset while the rest of the latches will be set. in addition, to maintain monotonicity an additional gate delay is selected in the cascade circuitry. as a result when d7 of chip #1 is asserted the delay increases from 31.75 gates to 32 gates. a 32 gate delay is the maximum delay setting for the e195. to expand this cascading scheme to more devices one simply needs to connect the d7 input and cascade outputs of the current most significant e195 to the new most significant e195 in the same manner as pictured in figure 1. the only addition to the logic is the increase of one line to the address bus for cascade control of the second pdc. set min set max to select multiplexers bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 d0 q0 len reset reset d1 q1 d2 q2 d3 q3 d4 q4 d5 q5 d6 q6 d7 q7 len len len len len len len cascade cascade figure 2. expansion of the latch section of the e195 block diagram reset reset reset reset reset reset reset reset reset reset reset reset reset reset
mc10e195, mc100e195 http://onsemi.com 7 5.5 30 25 4.7 20 15 15 4.5 4.9 5.1 4.3 v ee , (v) delay variation (ps) 10 5 0 5 10 5.3 0 1600 1575 40 1550 1525 1375 50 30 20 60 1500 1475 1450 1425 1400 10 1350 1325 1300 70 80 90 100 temperature ( c) figure 3. change in delay vs. change in supply voltage figure 4. delay vs. temperature (fixed path) propagation delay (ps) 0 4400 4300 40 4200 4100 3500 50 30 20 60 4000 3900 3800 3700 3600 10 3400 70 80 90 100 figure 5. delay vs. temperature (max. delay). temperature ( c) 064 2000 32 96 3600 2800 1200 128 figure 6. 100e195 temperature effects on delay. tap delay propagation delay (ps) propagation delay (ps) 85 c 0 c 040 88 50 30 20 60 84 80 76 72 68 10 64 70 80 90 100 figure 7. delay vs. temperature (per gate). temperature ( c) 040 20 60 3900 3400 2900 2400 1900 1400 80 120 100 figure 8. e195 delay linearity. tap selection propagation delay (ps) delay (ps) note: all taps selected set = h, temp. = 0 c
mc10e195, mc100e195 http://onsemi.com 8 figure 9. typical termination for output driver and device evaluation (see application note and8020 termination of ecl logic devices.) driver device receiver device qd 50 50 v tt q d v tt = v cc 2.0 v resource reference of application notes an1404 eclinps circuit performance at nonstandard v ih levels an1405 ecl clock distribution techniques an1406 designing with pecl (ecl at +5.0 v) an1503 eclinps i/o spice modeling kit an1504 metastability and the eclinps family an1568 interfacing between lvds and ecl an1596 eclinps lite translator elt family spice i/o model kit an1650 using wireor ties in eclinps designs an1672 the ecl translator guide and8001 odd number counters design and8002 marking and date codes and8020 termination of ecl logic devices
mc10e195, mc100e195 http://onsemi.com 9 package dimensions plcc28 fn suffix plastic plcc package case 77602 issue e 0.007 (0.180) tl -m s n s m 0.007 (0.180) tl -m s n s m 0.007 (0.180) tl -m s n s m 0.010 (0.250) tl -m s n s s 0.007 (0.180) tl -m s n s m 0.010 (0.250) tl -m s n s s 0.007 (0.180) tl -m s n s m 0.007 (0.180) tl -m s n s m 0.004 (0.100) seating plane -t- 12.32 12.32 4.20 2.29 0.33 0.66 0.51 0.64 11.43 11.43 1.07 1.07 1.07 2 10.42 1.02 12.57 12.57 4.57 2.79 0.48 0.81 11.58 11.58 1.21 1.21 1.42 0.50 10 10.92 1.27 bsc a b c e f g h j k r u v w x y z g1 k1 min min max max inches millimeters dim notes: 1. datums l, m, and n determined where top of lead shoulder exits plastic body at mold parting line. 2. dim g1, true position to be measured at datum t, seating plane. 3. dim r and u do not include mold flash. allowable mold flash is 0.010 (0.250) per side. 4. dimensioning and tolerancing per ansi y14.5m, 1982. 5. controlling dimension: inch. 6. the package top may be smaller than the package bottom by up to 0.012 (0.300). dimensions r and u are determined at the outermost extremes of the plastic body exclusive of mold flash, tie bar burrs, gate burrs and interlead flash, but including any mismatch between the top and bottom of the plastic body. 7. dimension h does not include dambar protrusion or intrusion. the dambar protrusion(s) shall not cause the h dimension to be greater than 0.037 (0.940). the dambar intrusion(s) shall not cause the h dimension to be smaller than 0.025 (0.635). view s b u z g1 x view d-d h k f view s g c z a r e j 0.485 0.485 0.165 0.090 0.013 0.026 0.020 0.025 0.450 0.450 0.042 0.042 0.042 2 0.410 0.040 0.495 0.495 0.180 0.110 0.019 0.032 0.456 0.456 0.048 0.048 0.056 0.020 10 0.430 0.050 bsc -n- y brk d d w -m- -l- 28 1 v g1 k1
mc10e195, mc100e195 http://onsemi.com 10 notes
mc10e195, mc100e195 http://onsemi.com 11 notes
mc10e195, mc100e195 http://onsemi.com 12 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indem nify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and re asonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized u se, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employ er. publication ordering information japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. mc10e195/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com n. american technical support : 8002829855 toll free usa/canada

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